I've found the exact timing of the bus turnaround should not be too critical - assuming you have a correctly functioning RS485 bus. In the instance where the TI gets triggered midway through the stop bit - disabling the 485 driver should allow the bus to settle in the idle state (assuming we have the requisite bias resistors and termination) thus maintaining the stop bit (as seen by the receivers). Some protocols can ignore junk characters if the bus isn't biased correctly (also max485's behave differently to most other '485 chips with an unbiased bus) but since I use Modbus RTU a lot, it uses character timeouts to mark the end of message. If you get junk chars due to an unbiased bus, the message fails. The only cpu I had troubles with RS485 with was the Z180 as the designers forgot to add an interrupt on the uart shifter being empty (or even a status bit) thus the interrupt happened on the holding buffer being empty and there was still a character being shifted out. What a pig it was. Zilog did fix it in the Z180S (they also has different mask versions that worked slightly differently). As for most other micros with inbuilt uart, there's not much of an issue.