hi Jay,
You may know that for clocked CMOS and mainly for VLSI CHMOS ,Vcc
decoupling is crutial as it draws current in extremely sharp spikes at
the clock edges the VHF and UHF components of these spikes are not
drawn from the power supply but from decoupling cap if the decoupling
circuit is not sufficiently low in inductance ,Vcc will glitch at each
clock edges and this could cause a misfunctioning of the memory device
I think thats why you were objected your subcontractor looks like
a person who goes by the book.You know in practical life we dont
give that attention to such things a 0.1uf capacitor is enough for us
(depending on how it is placed and your pcb design)see Jay you subcontractor
is now thinking like an engineer :)
and rest MrSchmitt has nicely explained from his very 4th line and
onwards.


sanjeev