Steve, they are !
as a hw engineer, i am responsible for developing HW and doing all EMC stuff (now it is the R & TTE in europe). i do all layouts. i have the knowledge of making a very high density pcb with analog amplifiers that have a gain of more than 100dB !! with CPU around it that works at 48MHz.

i have been on several add on courses for engineers that do emc oriented pcb design. there is also a mailing list at sun where pcb designs is discussed with digital signals of 600MHz and higher. there are the guru's that to the research why this is so and they find the formulas how to alculate that. they talk about currents in vias and what inductance the via has (how much pf would you expect?)

i have written some papers about this as a guideline for our company and all the others that work for the same owner. we calculate each capacitor. we calculate were it has to be placed.

if you use an 0805 smt cap and do a realy good layout (having the vias in the inner side of the cap going directly to the power plane, placing them on the outter side of the pads is wrong in emc behaviour), you will have some extra 20nH that comes from the metal contacts of the cap.
if you do an ac analysis of the cap, considering R,L,C and do a plot of Z against f you will see that this 100nF will have its lowest Z at around 5MHz and beyond this point it is only inductive. 100nf is capacitive until 5MHz, at 5MHz it is resistive, after this it is inductive.

this is physics. so you need to place more than one cap (but not several times 100nF, as this would only decrease Z) but place some caps with different values. looking at the plot again, you will see that now you have more than 1 resonance point. having calculated values, you can make shure that Z will be lower than a desired value for a frequency range higher than 5MHz. it is nor problem calulating these cap-arrays to give a Z lower than 1R for frequenies higher than 500MHz !
to make it clear, Z will be lower than 1R over the whole range (1MHz to 500MHz). We usually have power planes with Z < 1R

some app notes regardless who is the company who has done it, are absolutly wrong when looking in EMC on it. Yes you need cap's but they only thing in "DC". if you think in AC and in EMC you will see this differently. i have changed one layout, no component move or change. just the layout, looking at it with EMC-eyes. i was able to have a analog performace gain of 30% and a much lower emc emmision ! i was able to remove the metall shielding surround the pcb and the digital part did not interfere with the analog part (gain 100dB) that has impressed me much, and started to learn as much about it as possible. and it startet to make fun. if you know where to look at, what kind of easy winners you can have ... hey emc is fun !

and caps can be pure inductive.

regards.