I assume you're using only one NAND flash chip?

Presumably, the NAND data I/O pins can share with your SRAM's data pins and both connect to P0. Of course ALE will latch the SRAM's lower address byte from P0 and P2 will drive its upper address byte. Use pins from P1 or P3 to handle the NAND flash chip's WE\, RE\, CE\ (if necessary), ALE (don't connect to the 8051's ALE!), CLE and WP\ (if you care). Pull up RB\ (ready/busy) and connect it to the external interrupt pin. So, you'll need at least four NAND flash controls (RE\, WE\, ALE, CLE, with CE\ always low and WP\ always high) and a fifth (RB\) if you want to avoid waiting in a loop for things to happen. Yeah, this is the bit-bang approach; basically to write you drive data on P0 (perhaps with ALE or CLE), then assert WE\, then remove WE\. For reads, you simply assert RE\, wait the 20 ns or so read access time, read P0, remove RE\, lather, rinse, repeat.

You could also use the micro's OE\ and WE\ pins to drive the NAND's RE\ and WE\ lines and use external memory accesses to read and write but you'll have to ensure you don't conflict with SRAM access and maybe you'll need some glue logic. In any case, it's not that hard to handle.

-a