| ??? 07/03/06 08:11 Read: times |
#119539 - Thank you -Glue Logic Responding to: ???'s previous message |
Thank you Andy. I will connect flash I/O pins on P0, I already taught to do like that. I do not understand what do you mean by this "CLE and WP\ (if you care)". OK for WP\, but If I do not use CLE, flash will always be selected and because I am going to use same pins (P0) of micro for flash and for low adress of SRAM, and for LATCH (74HC573-several, for some other signals), there could be problems with data of flash, or not?
Please help me with glue logic. Thank you in advance for your help. By |
| Topic | Author | Date |
| AT89C51SND1C to NAND Flash | 01/01/70 00:00 | |
| what does P1 have to do with memory addr | 01/01/70 00:00 | |
| Mistake with P1 and P0 | 01/01/70 00:00 | |
| well since you will not say it | 01/01/70 00:00 | |
| Are you sure?? | 01/01/70 00:00 | |
| NAND flash pinouts | 01/01/70 00:00 | |
| NAND interface | 01/01/70 00:00 | |
| Thank you -Glue Logic | 01/01/70 00:00 | |
| NAND control | 01/01/70 00:00 | |
Thank you Andy | 01/01/70 00:00 |