You've answered your own question! There's no magic needed. Yes, you need to start the interrupts rolling by putting a char into the SBUF and clearing TI. How do you do it? Pretty much as you've described using the fifo_empty flag.

Also, reading your code (read the noob text on posting code - keeps the formatting and makes the code easier to read) in your isr you do not save the PSW or ACC or R0 for that matter. Not doing this will cause you much problem.

isr:
push PSW
push ACC
mov a,r0
push ACC ;you can push 0h, but this assumes only register bank0 is selected! Doing it this way saves R0 in the current register bank

...
...

pop ACC
mov r0,a
pop ACC
pop PSW
reti

8051's do not save anything apart from the program counter with interrupts - you have to do this and you can choose what to save. You also have the option of selecting another register bank (there are 4 of them) which makes for fast isrs.


Also you ignore the concept of atomicity. An interrupt can happen at any time (this is why we have interrupts!), like here:

mov a, TX_BUF_HEAD
xrl a, TX_BUF_TAIL
JZ TX_BUF_EMPTY_TEST

What happens if the serial interrupt happens between line1 and line 2? And the interrupt modifies tx_buf_head? Your code will make the wrong decision! And randomly at that. you need to disable interrupts whilst you test/modify these values then re-enable them once you've finished. Obviously you turn the interrupts off for the least amount of time. This avoids the 'race' conditions you talk of. This is no different for just about any cpu you care to name.