If you're wanting devise a one-time test to ensure there are no obvious defects in your memory IC's, you'll want to proceed in one way, and if you just want to ensure that there's read-write memory "out there" you'll want to go another, since the former may take several minutes.

A thorough one-time test will look for stuck bits, address-data interaction (data in one region of the memory is affected by where it is located), internal logic failure (e.g. a write to one region affects data in another), and perhaps a number of other tests about which there is considerable prior art.

A power-on self-test will just do what you've already done.

The power consumed in a CMOS device is normally very low, i.e. the quiescent power consumed is nearl negligible, despite the device performance. However, a fast memory cycled very fast will use more power than a similar memory cycled slowly. There shouldn't be much difference between a 120 ns CMOS memory cycled at a 120 ns rate and a 15 ns device like yours, so it's not much to be concerned about, though it may be somewhat more in the faster device.

RE