| ??? 04/23/07 15:22 Read: times Msg Score: +2 +2 Good Answer/Helpful |
#137816 - try not to confuse beginners... Responding to: ???'s previous message |
Mike Stegmaier said:
I know in reality that an 8051 doesn't use a segment:offset routine, but the reason why I explained it like that is because I was explaining what DPTR is and how it works. ........... ........... and for you x86 users, high byte and low byte is like the "segment and offset". No, it is not. again, from the link I provided: ******** Quote *********** Both the segment and offset are represented by a 16-bit number, allowing each segment to be 2^16 bytes in size (i.e., 65536 bytes, or 64 KB). This would seem to suggest that the 8086 can address up to 2^32 bytes, or 4 GB, since 32 bits are used for each address. This is NOT the case. When the processor obtains a logical address (segment and offset), it performs a simple calculation to determine the 20-bit physical address in memory to which the logical address refers: physical address = (segment << 4) + offset ********* Unquote ********** The DPTR is a SINGLE 16-bit register, but in order to manipulate it on an 8 bit processor, you need to address it as 2* 8bits, conveniently referred to as DPH and DPL. It is the same register however. DPH, DPL and DPTR are NOT 3 SFR's as you stated. How do people that use x86 processors be able to use MMIO on x51 processors if I didn't put that explanation? As far as memory mapping is concerned, memory mapped i/o on an x86 architecture has the same basic principle as on an 805x architecture. The I/O registers are addressed as "memory locations" and can be found in the memory map, next to ROM and RAM... No matter how the address is composed. regards Patrick |
