Erik,

I chose 8 bit access between the 8751 and the DRAM array while implementing a 16 bit path for an ADC & DAC. If i did it again i would probably just generate a separate CAS for each 8 bit bank (for the '51) to save xcvrs.

Reviewing one spec;
http://www.syncmax.com/PDF/speci...M16044.pdf

Look's like CAS is parallel'd to all chips so 4 xcvr's would be required.

Miroslav, is it the 32 bit width or the 128M depth (for little $$) you are after ?

Recent posts refer to the Triscend E5, perhaps it would implement this technology in far fewer parts (the refresh could be hardware instead of software).

regards,
p