mahmood Elnasser wrote:
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"Peter is mistaken here about pics, its true that there is one interrupt vector and you have to poll the interrupt flags to see which interrupt to service but there is no chance of missing interrupts because when one interrupt is serviced the isr will not go back to the forground program as long as another (enabled) interrupt flag is set."

No, I mean the Scenix SX18, which looks impressive with its 100MIPS at first. It looks near the PIC12C509.

But this SX18 has no timer interrupt pending flag. So if the interrupt was entered and no external interrupt pending bit was set, then the interrupt was caused by the timer.
But if any external interrupt pending bit was set, then you know no longer, if the interrupt was entered by an external interrupt or by an timer overflow some clocks earlier or later. So if you handle timer overflows only, if no external interrupt pending bit was set, you must lost some timer overflows short before and immediately after any external interrupt.

I searched now for the SX18 and get only old datasheets (1998). Maybe the SX18 was discontinued because this big mistake.

And I know not, if this was the only PIC derivate with such a strange behaviour.

I was only interest because the announced 100MIPS at 100MHz e.g. to solve tasks, which realized with CPLDs today.
So I have never looked on the other PICs.


Peter