Alan;
In his 8051/latch/eprom/display configuration the latch was required for addressing the eprom. The bigger differences I feel are the speeds of the microcontrollers. A normal 8051 tops out at 12Mhz with 12 clocks per machine cycle. The P89c51RD2 tops out at 20Mhz with 6 clocks per machine cycle. I'm guessing that Peter is using WR* to clock his display and with his new configuration the WR* pulse may be too short for the display to use. There seems to be a bit of confusion as to which memory Peter is referring to when he noted nearly 8k of onboard RAM. The datasheet says 1k of RAM and 64k of Flash. I'm uncertain where the 8k figure came from.

Hal