Cory:
I do not know if this helps but when Dallas or another manufacturer says that a part has its outputs "characterized" at loads of 80 pF or 100 pF what that means is that they mmeasured (and guarentee) the output timing specs in regard to rise times, fall times, pulse widths, and time delays at the specified load(s).

It does not mean that the part is unusable if the bus load capacitance is more than the characterized load.

Thus when you said you were expecting to see the capacitance on your PC board be a little higher I would expect that your circuit will work just fine. (Now if you told me bus loading was 820 pF that would be quite another thing)

You will want to watch your layout of the PCBA to make sure that you have good routing in place. It is particularly good if the routing can be A->B->C->D for each net of the bus instead of an auto-routed nest on each bus line with each branching off in every which direction. With a 33 MHz processor a pwr/gnd plane is probably almost essential (but you probably already knew this). :<)

In regards the total bus loading you should concentrate on the two most critical items of timing to/from the processor (as long as you have a reasonable margin on the normal strobe pulse widths and cycle times). The times to investigate most carefully are the read data setup time coming into the processor and the write data setup time out to the RAM or other peripheral. Another timing that needs to be looked at, but is in my experience a lesser problem with '51 designs, is the tri-state off time of the external devices off the bus. Make sure that there is enough underlap such that a device is OFF OFF before another device has the attempt to turn on to drve the bus. Faults caused by this, if it is an issue in a design can be the most devious type and are very hard to trace down).

Michael Karas