I have two data FIFOs, an FPGA, a Dallas E1 transceiver, and another '573 latch.

Well, at least you could integrate the '573 into the FPGA, that would save a bit of load.

I really do not think you will have a problem, but here is a suggestion: if you can get by with 64k FLASH and 8k SRAM (the 128k you show seems to be the least one can get these days), drop the exterior memory and use a p89c668. You may even want to check the offerings from ST micro (see ad above) they go even higher in internal memories. Either of these solutions will free up P0 and P2 for straight port operations which should give you even more of an advantage.

Erik