Erik,

I have two data FIFOs, an FPGA, a Dallas E1 transceiver, and another '573 latch.

You bring up an interesting point that I could reduce the bus loading by integrating the FIFOs into the FPGA. That would force me to use a 3.3V(I/O) FPGA to get the density needed. If I use a 3.3V FPGA, I would either use the 80C323, losing the speed I am trying to preserve, or add interface circuitry to protect the non 5V tolerant FPGA. Real estate is at a premium.

Cory Spackman