The best way to handle this is to divide the frequency down by a known scale factor say by 65536 via a 16 stage counter/divider. Then you use the output and measure its period very accurately with the standard 8052 period measurement scheme.

To increase your accuracy, with a given 8052 timer measurement resolution just divide the input frequency by a larger factor.

In terms of implementation of such divider I would look at a CPLD. These routinely have clocking ratings up in the 250 -> 500 mHz these days. For example, a Lattice Semiconductor ispMACH 4032V operating at 3.3V can clock up to 400 mHz. This small device with 32 logic cells in a TQFP-44 package could make just the counter/divider that you need. Here is a link to the data sheet for this part -> ispMACH^TM 4000V/B/C/Z Family.

A case of point is that these Lattice parts program in circuit through a JTAG port. The programming for the CPLD can be done with the free downloadable ispLEVER / Starter software that you can get at the Lattice web site.

Michael Karas