Lee:
Clearly the CPLD could be made to do all kinds of things. Heck you could even put the measuring counter into the CPLD and have a direct logic output to drive an LCD glass with the desired display numbers.

I do see that it could be useful to have the counter be shorter in length as the input signal is lower in frequency. Oren mentioned that the lowest frequency he would want to measure was aroung 20 mHz. As such it might be nice to change the divide by ratio from 16/24 bits as suggested before to maybe 12/20 bits. It would be simpler in the CPLD however to just design the counter so that its outputs (at least the ones we would be interested in) are fed into a selector MUX and gated out to a single pin. This one pin could drive the timer gate on the 8051. When a different counter/divider range was desired the select controls to the MUX would simply be changed. These could be other 8051 port bits connecting into the CPLD or the CPLD could have a register programmed through an external memory address if the 8051 was setup for an XRAM bus.

There is an incentive to having the high frequency counter/divider in the CPLD be the simplest logic possible. If you configure the counter to simply be a cascade of divide by 2 flip-flops then it is most likely that one can utilize the frequency rating of the CPLD. However once you make the logic more complex, such as building in a variable count/divider modulus, it may not be possible to get the circuit to work all the way up to the maximum frequency rate of the CPLD.

The manufacturers of CPLDs of course want to advertise a rating like 400 MHz for their CPLD. However the minute that you move the control terms for the flipflops through a stage or two of logic cells then the max rating for the flipflops with the feedback paths taken into account may be less than the rated F_max of the CPLD.

Michael Karas