Oleg:
I can send you via email the analysis spread sheet if you really want to see the details. The problem with the timing is most serious on the PSEN read cycle which is tighter than the the normal RD cycle. In this customers design there is a need to OR the active low level of the PSEN signal with the active low level of the RD signal so that the FLASH can be programmed and read in circuit. So that introduces a delay which agrivates the data release time to the microcontroller. There is also an address latching mechanism that is inside a Xilinx CPLD which takes time out of the address access time of the FLASH chip. Note that there were multiple timing parameters that were failing with parts that were too slow. I have found that the P87xx Philips part needed FLASH @ 55 nsec and SRAM at 45 nsec in order to run full speed at 16 MHz and properly meet all timing parameters.

When I commit a product to worst case timing analysis it is not sufficient to say that "the main timing consideration is ...", every timing pararameter must be satisfied.

This customer also made design changes after I pointed out some problems in the way he had the CPLD designed. For example I moved the OR of PSEN and RD out of the CPLD which had a 9 nsec delay and used an external single logic gate part that had a spec of 3 nsec.

The client is now going to look at using a P89LVxx type part becasue the Philips sales people told them not to use OTP parts as the while industry is going to FLASH. (I tried to tell them that 4 months ago but they did not want to listen.....arggh). The P89 series part has somewhat better timing characteristics and several of the timing parameters relative to PSEN were changed in how they are specified.

Michael Karas