Dear Raghunathan,

interesting, you store the information with falling edge of /WR.
I think Russell hit the nail. There's not enough setup time for the HC374, when the rising edge arrives at its clock input:

First we analyze situation with 12clock mode:
Propagation delay time through HC245 can be up to 21nsec. Setup time of HC374 is 20nsec minimum. So, rising edge at HC374 is not allowed to come earlier than 41nsec after data has stabilized at port pins.
Falling edge of /WR comes >=53nsec (tQVWX) later than data has stabilized at port pins. Also there's 15nsec propagation delay time through HC138 and 8nsec through inverter (HC04 assumed). Makes 76nsec.
So, there should be a headroom of 76nsec - 41nsec = 35nsec.

Now for 6clock mode:
Falling edge of /WR now comes >=17nsec later than data has stabilized at port pins. Now 17nsec + 15nsec + 8nsec = 40nsec. And 40nsec - 41nsec = -1nsec! So, rising edge at clock pin of HC374 comes 1nsec too early.

Although such pseudo-exact caluclations are always rather questionable, because propagation delay times depend on many factors, especially on actual capacitive load at outputs, it states, that there's not enough headroom with your timing. Also, if you have a cable introduced in signal routing, timing can additionally be eroded, if transmission line effects become to play a role.

I would add some more inverters (HC04) at clock pin of HC374. Choose of 'good old' CD4049 is NOT recommended, because /WR pulse is rather narrow at 12MHz in 6clock mode, I think 140nsec.
In such a situation, some persons insert between inverter output and clock input of HC374 a resistor of 1kOhm and from clock input of HC374 to ground a small capacitance of 18pF (NP0). Together with maximum stray input capacitance of 10pF this gives a time constant of 28nsec and a rise time of 2.3 x 28nsec = 64nsec. Others think (hallo Erik!) that introducing of such RC-filters is not an elegant methode...

Also, use of FRC with grounded wire between data lines and clock line is highly recommended. If you must route also the +5V voltage, the according wire should not be routed next to clock line or any data line! Otherwise, switching noise of HC374 on Vcc can erroneously fedback to clock line or data lines and cause false triggering.

Good luck,
Kai