I was always told that creating a delay with R & C was BAD! As to why that is so I was never told.

Hallo Russell,

may be we should discuss this issue a bit? Have a look at the following schematic:



As you stated, some decades ago, RC delays were widely used. And they made trouble from time to time! There are several reasons today not to use RC delays. Here the two most relevant:

1. RC delays do not only work as a delay line, but they also heavily increase transition time of edges. They lead to a heavy decrease of slew rate. Means, if the first inverter in above schematic toggles his output, at input of second inverter, point X, a signal can be observed with much much lower slew rate. If we take e.g. R = 4.7kOhm and C = 30pF (including input stray capacitance), then time constant is 141nsec. This leads to a rise or fall time of 2.3 x 141nsec = 324nsec. The major disadvantage of decreased slew rate is now, that over a much longer period input signal is dangerously close to threshold level of gate. So, whenvever a level transition occurs, for a period of 100...200nsec very small interference and noise is sufficient to cause mistriggering!

In some databooks maximum input rise and fall times are specified. For CD4000 series this is about 15µsec and for HCMOS about 500nsec. Now one could think, that our above RC delay with 324nsec rise and fall time is quite acceptable, even with HCMOS. Right?
No! 500nsec is the value which, when being overanged, leads to an heavily increased danger of occurence of automatic self oscillation! Means, if rise and fall time is greater than 500nsec, then oscillation can occur, when input voltage comes close to threshold level. This self oscillation can occur even in the absence of external noise and interference, only by chip internal feedback! That's why it's called 'self' oscillation.
But even with rise and fall times being much smaller than 500nsec, such mistriggering can occur, as I stated above, then for instance caused by noise or interference coupled into point X.
Whenever signal toggles, for the period of rise or fall time, gate, which is following the RC delay is in a 'state of emergency'.

Now one might think, that with Schmitt-trigger gates all is fine. But, this Schmitt-trigger will mainly help to suppress 'self oscillation'. And although there is a certain hysteresis introduced, again a certain danger of mistriggering is present, if voltage at input is far away from 0V or +5V, means if input voltage is near the middle of supply voltage.

2. The major 'tool' to suppress noise with fast digital CMOS chips is their low output source impedance. If a standard HCMOS gate emits high level (re low level), pMOSFET (re nMOSFET) of output stage looks like resistance of about 50Ohm connected from +5V (re 0V) to output. So, if noise is coupled into the connection between the output of one HCMOS gate and the input of another HCMOS gate, then this noise is shunted to ground via a path showing an impedance of about 50Ohm. But with RC delay, situation looks different. Assume that in above schematic noise and interference is coupled into point X. Then, this 50Ohm path is no longer present! For frequencies between 0Hz and 1/2/pi/R/C, in our example about 1MHz, only the very high impedance of about 4.7kOhm, which is about 100 times higher than 50Ohm, will 'help' to shunt noise and interference to ground.
Ok, capacitor C will present a much lower impedance at higher frequencies. But impedance of C will equal 50Ohm only at a frequency of 106MHz! At lower frequencies impedance from point X to ground is much higher than compared with the situation, where this RC delay is avoided.

Unfortunately, this worsened capability of suppressing noise by shunting via low impedance to ground increases danger of mistriggering, of course: 1. Heavily decreased slew rate drastically increases period, where input voltage is close to threshold voltage and noise can cause mistriggering, and 2. Suppressing noise is highly worsened due to drastically increased impedance from input to ground.

Not at all a good combination, when working with fast digital CMOS chips!

Kai