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???
02/13/04 08:06
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#64685 - RE: Memory IO issue
Responding to: ???'s previous message
Hi,
Kai,
But the main issue of your recommendation is to use the rising edge of /WR for latching, right?

Okay, my idea is: 74373/573 contains static D-trigers opposite to dynamic ones in 374/574. It does not need with an edge to latch data, it is level-activated. So the idea is that 373/573 accepts data during all the time WR is active. It starts to accept data at high level on pin 11 and stops when the level comes zero. As result it easy fixes "transition" effects as well as impulse hindrances on data lines especially for long wiring. Here we use such scheme for 1 meter FRC.

Regards,
Oleg

List of 18 messages in thread
TopicAuthorDate
Memory IO issue            01/01/70 00:00      
   RE: Memory IO issue            01/01/70 00:00      
   RE: Memory IO issue            01/01/70 00:00      
      RE: Memory IO issue            01/01/70 00:00      
   RE: Memory IO issue            01/01/70 00:00      
      RE: Memory IO issue            01/01/70 00:00      
         RE: Memory IO issue            01/01/70 00:00      
            RE: Memory IO issue            01/01/70 00:00      
               RE: Memory IO issue            01/01/70 00:00      
                  RE: Memory IO issue            01/01/70 00:00      
                     RE: Memory IO issue            01/01/70 00:00      
                        RE: Memory IO issue            01/01/70 00:00      
                           RE: Massive Ground Plane - Kai            01/01/70 00:00      
                              RE: Massive Ground Plane - Kai            01/01/70 00:00      
                                 A lesson learnt - Kai            01/01/70 00:00      
      RE: Memory IO issue            01/01/70 00:00      
         Discuss of RC delay            01/01/70 00:00      
            Memory IO - resolved            01/01/70 00:00      

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