Hallo Prahlad,

having a solid ground plane is much more important than having a Vcc plane! This is a direct consequence of the fact that for TTL compatible digital logic chips low voltage noise margin is smaller than high voltage noise margin.

Have a look at the following schematic:



It shows two idealized 74HCT00 gates sitting in different packages. The output of the left is connected to the input of the right. Both packages are separated by some distance, so that potentials at point 'A' and point 'B' need not necessarily to be identical. The same is valid for potentials at points 'C' and 'D'.

The both 74HCT00 gates need not necessarily to be members of 74HCT-family. They stand for typical TTL compatible CMOS logic chips, which produce at their outputs a rail-to-rail swing, means either ~0V or ~+5V, but expect TTL levels at their inputs, means either <0.8V or >2.0V.

Now let's introduce big noise on ground connection and Vcc connection of both chips above. Assume for instance, that on the left side of schematic there's another 74HCTMOS-gate, which is just switching from high level to low level, or vice versa. Then, for a very short period (about 1nsec) both output FETs, namely NMOS and PMOS are turned-on, causing a sharp spike current flowing from point 'D' to point 'C', to this just switching gate, through its Vcc connection running to its ground terminal, and finally back through point 'A', and then through point 'B'.

Even if this just switching gate has a decoupling capacitor next to it, there will flow a certain current as stated above. By the way, there are also other currents of spiky nature which will travel along ground connections and Vcc connections as well, even if power supply decoupling would be perfect.

Now assume, that these ground connections and Vcc connections are not made of solid planes. Then, there will exist tremendous inductivity along the paths joining the points 'A' and 'B' and points 'C' and 'D'. As consequence a heavy voltage spike will drop along these inductivities.

The important fact is now, that on Vcc connections we can alow bigger voltage drops than on ground conections. Because of different noise margins:

Have a look again at the third gate which is just switching. Current spike will cause, that potential at point 'C' will drop relative to point 'D'. As consequence, output of left gate (shown in schematic) will also drop. And finally input voltage of right gate will also drop. To which level we can allow the voltage here to drop? At high level condition, down to 2.0V. So, this voltage drop can be 3V without changing logic state of involved gates.
But, what about voltage drop between points 'A' and 'B'? If discussed spike current flows from point 'A' to point 'B', then potential at point 'A' will rise relative to point 'B'. As consequence, output of left gate (shown in schematic) will also rise. And finally input voltage of right gate will also rise by the same amount. To which level we can allow the voltage here to rise? At low level condition, up to 0.8V. So, this voltage drop between point 'A' and point 'B' must only be 0.8V maximum, if logic state of involved gates shall remain unchanged!

This is up to about 4 times smaller than the voltage drop that is allowed on Vcc connections!! So, inductivity of ground connections must be much smaller than for Vcc connections. And this is the reason, why having a solid ground plane is much more important, than having a Vcc plane.

Of course, this does not mean, that Vcc plane is unnecessary. Very fast digital circuits, can profit from them. But for standard microcontroller circuits running at clock frequencies lower than 12MHz, only containg 74LS- or 74HC(T)-chips, it's the solid ground plane which we need so urgently, not the Vcc plane.

By the way, it's amazing how 'solid' a ground plane can be made, if only a double sided PCB is used. It's not necessary all the time to take the multilayer board. Have a look at this example board (double sided PCB with solid ground plane):







Kai