"I am interfacing an 8052 with a National Semiconductor TP3054 audio CODEC. The CODEC has a master clock (MCLKx) that I am running with a 1.544-MHz oscillator. I plan to drive the CODEC's bit clock (BCLKx) with a port pin on the 8052, but according to the datasheet, the bit clock can be from 64kHz to 2.048MHz, `but must be synchronous with MCLKx'."

They way these things usually work is that there's a master clock and the bit clocks (and in some cases, LRCLK) and the data are synchronous to the master clock.

This is implemented by starting with the master clock and dividing it down to create the lower-frequency clocks. The divider is synchronous with the master clock, which means that everything changes with the master clock, and if you looked at the signals on a 'scope, you'll see that the bit clock changes some fixed clock-to-out time after the master clock. Basically, the bit clock must be "in phase" with the master clock. The serial data bits are synchronous with the bit and master clocks, too.

There's no way you can drive the bit clock from a micro port pin and have it synchronous with the master clock. You could use some flip-flops to divide it down as needed. (I've done this in CPLDs and it's quite simple.)

Perhaps you could explain what you want to do ?

--a