I have several designs using the slower SiLabs devices which are on a two-layer PCB (with a solid GND plane, naturally!). It is very well possible to 'immunise' such a design against EMI, especially if the number of traces (and their length) going to and from the controller is limited.

But for a design with the F12x family, I would not even think of a two-layer PCB and go straight for a 4-layer. Even more so in a design with such a lot of I/O's.

Another very important factor with these devices is decoupling. Their extreme speed calls for a liberal amount of decoupling with high quality capacitors. Any 'economising' in this area will come back to haunt you.


Rob.