| ??? 12/20/04 04:07 Modified: 12/20/04 04:16 Read: times |
#83471 - Thats not the solution. Responding to: ???'s previous message |
Dear Shivani,
replace 89s with 89c ,kuldeep was facing the same problem in his project 89c is worked fine in his case,although rc reset cause problems but they are not so bad that they cannot execute even on table No, Never replace AT89Sxx with AT89Cxx since AT89Cxx is outdated and not recommended for new designs. Fashid stick to AT89Sxx dont revert back to AT89Cxx. I am not sure if the problem is reset related. But if at all it is you should use a power supervisor instead off RC reset. You can use DS1232 MAX810 MAX812 etc. REPLACING AT89Sxx with AT89Cxx IS NOT THE RIGHT THING. Thus -1 from me. Dear Farshid, a. Read The above carefully and use a supervisor. b. Are you sure your micro is programmed. If not then you can see 0V at P0 pins if micro is trying to put state 0 on those pins. I had a quick look at your schematic and noted following potential prblems/ design mistakes, 1. Button inputs on P1.1 and P1.2 are pulled down to ground using a resistor and connected to Vcc directly through switch. This is not the right thing. With this setup you may damage the port pins when you press the switch. The correct way to interface such buttons is pullup to Vcc when open switch and connected directly to ground when switch pressed. If you find this text hard to digest let me know I will post a schematic. The same is true for DIP switch on P1.3 Remember micro port pin should never see a direct connection to supply. 2. You are feeding ALE to the ADC0808 CLK input. Datsheet of ADC0808 says following values for CLK MIN = 10KHz TYP = 640KHz MAX = 1280KHz You are using 11.0592 Crystal thus your ALE frequency is 11.0592/6 i.e 1.843MHz i.e 1843 KHz you are exceeding MAX clock frequency for ADC. I would use T2 CLKOUT for generating this clock frequency. 3. Using POT for VREF is not a good thing use LM336 or some other precision Vref source for this purpose. 4. I guess you are using EAGLE for schematic and PCB design. Tell me If I am wrong. In the schmatic you have drawn a box around Power Supply. This box appears to be drawn in Net Layer. It is not a good thing to use Net for such box drawing Use Symbols layer for this purpose. Ignore 4. If you are not using Eagle. Regards, Prahlad Purohit |
| Topic | Author | Date |
| invalid voltage on a pulled up/down Port | 01/01/70 00:00 | |
| replace s with c | 01/01/70 00:00 | |
| Thats not the solution. | 01/01/70 00:00 | |
| please follow the main problem | 01/01/70 00:00 | |
| and some news | 01/01/70 00:00 | |
| s51 is good | 01/01/70 00:00 | |
| Pullup/down | 01/01/70 00:00 | |
| Sorry for Echo. | 01/01/70 00:00 | |
| pull up/downs | 01/01/70 00:00 | |
| pullup+pulldown = potential-divider? | 01/01/70 00:00 | |
| Potential, potential divider? | 01/01/70 00:00 | |
| potential divider / where wires go | 01/01/70 00:00 | |
| blow it | 01/01/70 00:00 | |
| don't blowed it (atleast not untill now) | 01/01/70 00:00 | |
| where does the wires go | 01/01/70 00:00 | |
| To Erik and others | 01/01/70 00:00 | |
| This will not work with 'C51s | 01/01/70 00:00 | |
| Exactly | 01/01/70 00:00 | |
| just got the point :) | 01/01/70 00:00 | |
| And finally the problem solved! | 01/01/70 00:00 | |
| I meant ++hundreds of microampere++ | 01/01/70 00:00 | |
| Wrong question ! | 01/01/70 00:00 | |
| Negative Logic? | 01/01/70 00:00 | |
Yes, negative logic! | 01/01/70 00:00 |