| ??? 01/04/05 22:32 Read: times |
#84328 - AC "loading" Responding to: ???'s previous message |
Is the DC analysis the Ioh and Iol values and the AC analysis to do with the capactive loads?
The DC analysis is irrelevant unless your design is extremely strange. The capacitances apply not as "loading" but as "propagation delay modifiers". You can put a farad on the output of a CMOS gate, it will still eventually change. Erik |
| Topic | Author | Date |
| Worst case design | 01/01/70 00:00 | |
| bible time | 01/01/70 00:00 | |
| What about an example? | 01/01/70 00:00 | |
| loading analysis | 01/01/70 00:00 | |
| Laoding Analysis | 01/01/70 00:00 | |
| AC "loading" | 01/01/70 00:00 | |
| AC analysis | 01/01/70 00:00 | |
| AC loading | 01/01/70 00:00 | |
| Andy forgot | 01/01/70 00:00 | |
| Not so much | 01/01/70 00:00 | |
| How to post a schematic - Tutorial | 01/01/70 00:00 | |
| Analysis... | 01/01/70 00:00 | |
| Schematic | 01/01/70 00:00 | |
| ? | 01/01/70 00:00 | |
| new url | 01/01/70 00:00 | |
| Link | 01/01/70 00:00 | |
| Third time lucky | 01/01/70 00:00 | |
| the link | 01/01/70 00:00 | |
| Oh dear... | 01/01/70 00:00 | |
| Clock Freq. | 01/01/70 00:00 | |
| old school | 01/01/70 00:00 | |
| ADC | 01/01/70 00:00 | |
| 1997 | 01/01/70 00:00 | |
| ? | 01/01/70 00:00 | |
| Design Practices | 01/01/70 00:00 | |
| for the sake of it | 01/01/70 00:00 | |
| living in the past | 01/01/70 00:00 | |
| Old Design practice | 01/01/70 00:00 | |
| Call My Bluff? | 01/01/70 00:00 | |
| true meaning of "Worst-Case" | 01/01/70 00:00 | |
Are you sure? | 01/01/70 00:00 | |
| Business spec ? | 01/01/70 00:00 | |
| UniS? | 01/01/70 00:00 | |
| Naw | 01/01/70 00:00 | |
| Ya | 01/01/70 00:00 | |
| ? | 01/01/70 00:00 | |
| Try this | 01/01/70 00:00 | |
| can not answer | 01/01/70 00:00 |