As long as CMOS chips are used, DC loading isn't an issue, normally, unless you try to combine 3V circuitry with 5V one, for instance, or you insert impedances in series with inputs/outputs of microcontroller.
AC loading is often a question of capacitive loading. But as long as strong push-pull stages are driving the lines, a danger only exists, if capacitive load is heaviliy overranged. The datasheet tells you, when this is the case.
A problem arises if you try to drive lines by an 'open drain' driver circuit. Then, the pull-up resistance can be much higher than the typical source impedance of a standard push-pull driver (which is about 30...100 Ohm). In this case a low pass filter is formed by pull-up resistor and load capacitance, which can result in an extreme decrease of rise time and increase of propagation delay time of signal.
So, if your circuit contains 'open drain' drivers, then this is a point to be issued.


Have a look at application note 457 from Philips, which you will find here, for instance:

http://ece-www.colorado.edu/~mcclurel/pan457.pdf

This application note includes a nice timing analysis for the interfacing of external memory and will give you an idea, what a timing analysis should focuse on.

Keep in mind, that this '51 microcontroller is manufactured to easily work with several sorts of external hardware like SRAMs, EPROMs, latches, etc. So, the timing characteristics must have a certain headroom. But the faster the clock frequency goes the more the headroom shrinks and what might be easy at 6MHz clock frequency can become troublesome at 24MHz. So, whether timing is critical often depends on clock frequency of microcontroller.

And keep also in mind, that your 'loading and timing analysis report' will become the longer, the more unusual and exotic circuitry you add...

Kai