| ??? 01/05/05 17:07 Read: times |
#84406 - Not so much Responding to: ???'s previous message |
Erik said:
Often the capacitance of the trace(s) on your PCB will be more than the input capacitance of the chips. A piece of wire of 1cm length shows an intrinsic space charge capacitance of about 1.8pF. Even if you assume a rather extended bus routing of 20cm total length, this will only add less than 40pF. In most cases total load capacitance, input capacitance of chips included, will be well below 100pF. A relevant source of unexpected load capacitance can be the use of chips in ceramic packages, by the way... Kai |
| Topic | Author | Date |
| Worst case design | 01/01/70 00:00 | |
| bible time | 01/01/70 00:00 | |
| What about an example? | 01/01/70 00:00 | |
| loading analysis | 01/01/70 00:00 | |
| Laoding Analysis | 01/01/70 00:00 | |
| AC "loading" | 01/01/70 00:00 | |
| AC analysis | 01/01/70 00:00 | |
| AC loading | 01/01/70 00:00 | |
| Andy forgot | 01/01/70 00:00 | |
| Not so much | 01/01/70 00:00 | |
| How to post a schematic - Tutorial | 01/01/70 00:00 | |
| Analysis... | 01/01/70 00:00 | |
| Schematic | 01/01/70 00:00 | |
| ? | 01/01/70 00:00 | |
| new url | 01/01/70 00:00 | |
| Link | 01/01/70 00:00 | |
| Third time lucky | 01/01/70 00:00 | |
| the link | 01/01/70 00:00 | |
| Oh dear... | 01/01/70 00:00 | |
| Clock Freq. | 01/01/70 00:00 | |
| old school | 01/01/70 00:00 | |
| ADC | 01/01/70 00:00 | |
| 1997 | 01/01/70 00:00 | |
| ? | 01/01/70 00:00 | |
| Design Practices | 01/01/70 00:00 | |
| for the sake of it | 01/01/70 00:00 | |
| living in the past | 01/01/70 00:00 | |
| Old Design practice | 01/01/70 00:00 | |
| Call My Bluff? | 01/01/70 00:00 | |
| true meaning of "Worst-Case" | 01/01/70 00:00 | |
Are you sure? | 01/01/70 00:00 | |
| Business spec ? | 01/01/70 00:00 | |
| UniS? | 01/01/70 00:00 | |
| Naw | 01/01/70 00:00 | |
| Ya | 01/01/70 00:00 | |
| ? | 01/01/70 00:00 | |
| Try this | 01/01/70 00:00 | |
| can not answer | 01/01/70 00:00 |