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???
01/29/05 10:18
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#86098 - CPLD questions
Responding to: ???'s previous message

As for your questions regarding the output of the logic compiler - the best way is to observe it's output. Your different means of expressing the same logic should yield the same result! The compiler does not have black magic - it simply does the labourious work of interpreting and simplifying the logic - where it really comes into it's own is when doing state machines - doing the state transition tables takes time by hand, seconds with the compiler!

You can also use schematic capture as the input for your logic. For smaller projects this is my preferred input. Abel is better when doing state machines. Personal choice rules here. There's also VHDL and Verilog - this is a subject on it's own!


As for the propogation delay through one logic block - it is constant! Think about it - the 'and' 'or' array is a constant structure - the fuses only enable/disable the input signals into the logic. Now, if you use the output of one logic block to feed another logic block - then you have twice the delay (maybe minus to output buffer delay). In some of the large cplds you also have to contend with routing resources - these add delays. The output of the Xilinx logic fitter will tell you the worse case path delays. FPGAs are a different kettle of fish - the logic block in most fpgas is actually a small block of ram and the logic is solved by a lookup table approach. The compiler does the magic for you. Therefore most complex logic will use a few levels of these logic blocks and also routing lines. Depending on how the logic compiler decides to solve, route and place the logic determines the actual delay through a path. Again, the fitter will give you a report of all the paths and you can even specify a maximum delay on a path to force the sompile/fitter to work harder for you. Another way is to floorplan the device yourself - you place the logic block where you want them for the shortest path etc. It's a bit like manual vs autorouting a pcb - sometimes humans can do a much better job although it takes more time.

For people starting out with cplds and fpgas I would suggest:
XILINX STUDENT EDITION. isbn 0-13-671629-6. I got mine from Amazon.com. It comes with a book and xilinx software on CD. There's also a board you can purchase, but I went straight to my own pcb. I would highly recommend it. It answers all the above questions and more.





List of 18 messages in thread
TopicAuthorDate
CPLD/ABEL question/invitation            01/01/70 00:00      
   CPLD questions            01/01/70 00:00      
   ABEL questions            01/01/70 00:00      
   vell...            01/01/70 00:00      
   Minimisation            01/01/70 00:00      
      NP complete            01/01/70 00:00      
   Answer to the third question            01/01/70 00:00      
   CPLD headstart (ppt)            01/01/70 00:00      
   New questions            01/01/70 00:00      
      new answers            01/01/70 00:00      
         JTAG pull-up            01/01/70 00:00      
            re: JTAG pull-up            01/01/70 00:00      
   NP completness            01/01/70 00:00      
   basic error            01/01/70 00:00      
      Eric            01/01/70 00:00      
   How to Build a Jtag Cable            01/01/70 00:00      
      pegboard            01/01/70 00:00      
   jtag cable            01/01/70 00:00      

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