First, I've gotta say: if you're getting into programmable logic, I highly recommend forgetting about ABEL. Rather, flip a coin and choose to learn either Verilog or VHDL. (Or both.) CPLD/FPGA vendors Brand A and Brand X both offer free versions of synthesis tools and the ModelSim simulator.



ABEL is basically assembly language and its output will be whatever you give it. There may be some product-term collapsing but minimization is very minimal.

As for your examples, they are just different ways of writing the exact same thing, so the result will be identical.



Ah, don't forget that after the ABEL compiler does its job, its output is handed to the place-and-route tools. There are various fitter features that can indeed give you different results from identical code. For example, just change your pins! Or, change the seed that is used to start the placement process. Or change your timing constraints. The result is guaranteed to be logically and functionally equivalent, but if your fit ends up using different resources in the chip, the fuse map and the checksum and such will not be identical.



ABEL won't do that, but the fitter will, and the fitters are really good these days.



Yes, ABEL will DeMorganize as necessary.



It depends on the function and the routing and the placement of the logic blocks within the device. You really need to look at the data sheets and see how each device handles large logic functions. If an equation only has a couple of inputs, then it will be faster than one that requires more product terms than the logic block normally supports. The large logic functions will "Borrow" product terms from nearby logic blocks and there will of course be additional delays.

If you really need the outputs to change at the same time, the answer is obvious: synchronous design and make sure the output flops are in the I/O block.

--a