The logic synthesis tool perform a variable amount of logic minimisation and the amount performed depends on the goals that you set the synthesiser,you can set it to produce the smallest implementation,or the fastest,or the safest for statemachines getting stuck in unknown states etc and so on.There is no known way of telling if some logic function has the minimum number of logic terms or is the fastest or any other metric other than simply trying lots of different solutions and seeing which meets the design goals,and actualy fitting logic into a FPGA or CPLD is what is called a NP complete problem so again its a matter of trial and error until you hit some goal.