First question: why not use something more modern? CoolRunners or Altera MAX or Lattice isp5000VE?



Are they unused? If so ... although I would carefully read the docs; perhaps there's a fitter option you can use to either pull the inputs up or down internally, or configure them as outputsin which case, you don't wanna ground 'em). I know that more modern chips let you do this. It's been quite awhile since I did a 9500 design.



If the pins are not used in the design, then do as the documentation says. Remember WHY you ground unused CMOS inputs!



I would make sure that the header you put on your board matches the cable you wish to use. Otherwise, you'll be using fly-leads, which are do-able but annoying.

Also, you need to make sure the JTAG/ISP signals are pulled up or down as required, so when the cable is disconnected, your chip doesn't decide that it wants to enter programming mode.



Most regulars on comp.arch.fpga think that Xilinx is waaaay too conservative when it comes to bypassing requirements. I typically use a 0.1uF for each power pin, and perhaps one or two 10 uF tantalum bypasses near the chip. It's also a Real Good idea to have power and ground planes.

--a