Nobody uses ABEL these days as its almost impossible to tell what the hell is going on with it as you noticed,so vhdl/verilog is the way to go.
The question of wether the synthesis tool has generated what you expected is a difficult one because once you start working with vhdl for example you will find that it is very strongly typed and it is very easy to write vhdl code which is either ambigious,ie the synthesis tool can find several solutions which match the logic specified,or the code has no possible way of being synthesised in actual hardware,or what you expect the code to mean to the synthesis tool just doesnt mean what you expect,although there are standard implementations for vhdl people are still arguing about some of the more arcane aspects.Remembering that vhdl is first and foremost a simulation language and the synthesis bit has been bolted on at a later date.So what even people who design fpga/cplds for a living do is check that the physical logic generated is the same as the model by doing simulations with both the vhdl and the synthesised logic,hopefully they will be functionaly the same.