| ??? 03/13/05 16:18 Read: times |
#89579 - Not true ! Responding to: ???'s previous message |
Erik Malund said:
When bitbanging you can not afford interrupts or anything, all resources must be dedicated to the bitbang while it goes on. Thats not true ! I2C is fully synchronous. So the master I2C need never to disable any interrupt, because the slave is awaiting the next state after the next SCL clock. So it plays no role if any I2C transfer was done at maximum speed or with only one clock cycle per second. There are only minimal timing requirements inside the I2C specification but no maximum timings. The speed advantage of a hardware I2C became only significant, if the CPU load of a software I2C increases over 10%. E.g. driving an I2C text display every 200ms was far below any meaningful CPU load. Also the spead advantage of hardware I2C can only be seen, if it was fully interrupt driven. On simple busy waiting the speed advantage was exact zero. Peter |
| Topic | Author | Date |
| 89C66x and 89C51RD2 | 01/01/70 00:00 | |
| hw IIC vs bitbang | 01/01/70 00:00 | |
| can u illustrate/elaborate wth some code | 01/01/70 00:00 | |
| rate does not matter | 01/01/70 00:00 | |
| Not true ! | 01/01/70 00:00 | |
| Total Agreement | 01/01/70 00:00 | |
| what about XRAM? | 01/01/70 00:00 | |
| XRAM and mnufacturers | 01/01/70 00:00 | |
| XRAM, more | 01/01/70 00:00 | |
| SW-I2C mostly sufficient ! | 01/01/70 00:00 | |
| similar CPU load?? pray explain | 01/01/70 00:00 | |
| "...significant advantage..." | 01/01/70 00:00 | |
| how do you do soft IIC with 1% load | 01/01/70 00:00 | |
| 1% = | 01/01/70 00:00 | |
| Peters 1% | 01/01/70 00:00 | |
| very high data rates?? | 01/01/70 00:00 | |
| consider the whole program ! | 01/01/70 00:00 | |
| Its really very high. | 01/01/70 00:00 | |
| how can microresistance | 01/01/70 00:00 | |
| Forum rules - no SMS | 01/01/70 00:00 | |
the skinny | 01/01/70 00:00 | |
| sorry for the informal language | 01/01/70 00:00 |