| ??? 03/13/05 17:04 Modified: 03/13/05 17:10 Read: times |
#89583 - "...significant advantage..." Responding to: ???'s previous message |
@Erik,
on my view a CPU load of only 1% was almost similar to 0.5%. Especially for only 1% load there is no need for using interrupts and then both ways are exact equal. The trick on efficient programming was, do only such improvements which give significant results ! Please read the whole post. I stated already "very high data rate" can profit from the hardware I2C. Peter |
| Topic | Author | Date |
| 89C66x and 89C51RD2 | 01/01/70 00:00 | |
| hw IIC vs bitbang | 01/01/70 00:00 | |
| can u illustrate/elaborate wth some code | 01/01/70 00:00 | |
| rate does not matter | 01/01/70 00:00 | |
| Not true ! | 01/01/70 00:00 | |
| Total Agreement | 01/01/70 00:00 | |
| what about XRAM? | 01/01/70 00:00 | |
| XRAM and mnufacturers | 01/01/70 00:00 | |
| XRAM, more | 01/01/70 00:00 | |
| SW-I2C mostly sufficient ! | 01/01/70 00:00 | |
| similar CPU load?? pray explain | 01/01/70 00:00 | |
| "...significant advantage..." | 01/01/70 00:00 | |
| how do you do soft IIC with 1% load | 01/01/70 00:00 | |
| 1% = | 01/01/70 00:00 | |
| Peters 1% | 01/01/70 00:00 | |
| very high data rates?? | 01/01/70 00:00 | |
| consider the whole program ! | 01/01/70 00:00 | |
| Its really very high. | 01/01/70 00:00 | |
| how can microresistance | 01/01/70 00:00 | |
| Forum rules - no SMS | 01/01/70 00:00 | |
the skinny | 01/01/70 00:00 | |
| sorry for the informal language | 01/01/70 00:00 |