This morning I stepped away from the Xilinx tutorials a tiny bit and tried to make a 1 KHz, 20% duty cycle signal by dividing down the 50 MHz clock that's on the eval board. Here's the essence of what I came up with:

    reg [15:0] clockDivider;                // A 16-bit counter
    reg outputBit;                          // 1 KHz, 20% duty cycle signal

    always @(posedge clock50Mhz) begin      // On 50 MHz clock rising edge
        clockDivider = clockDivider + 1;    // Bump the counter
        if (clockDivider == 50000) begin    // One millisecond has gone by
            clockDivider = 0;               // Reset the counter
            end                             // End 'one msec has gone by'
        outputBit =                         // Assert the output for 20%
            (clockDivider < 10000) ? 1 : 0; //  of the one ms period
        end                                 // End 'on 50MHz rising edge'

This works fine; the waveform on the physical output pin looks exactly as expected. However, I realized as I was fiddling around that you could get the same result in many, many, many different ways.

Eventually, I suppose I'll be able to evaluate various ways of doing things by looking at what the synthesizer produces, but I haven't figured out exactly what to look for yet. So in the meantime, I'll ask you guys for a simple sanity check. Is my approach here at least somewhat reasonable? Or are there perhaps other ways to do the same thing that are wildly better in one way or another?

-- Russ