I've come across what seem to be two alternate ways of arranging the logic in a simple Verilog module. One way puts all the logic into a single always block, with a bunch of ifs inside it to sort out what to do when. The other way seems to break up the logic into little chunks and puts each chunk into its own always block. Here are a couple of do-nothing examples that show generally what I am talking about:

module OneWay (input clock, reset, rd, wr);
    always @(posedge clock) begin
        if (reset) begin
            /* Misc reset stuff */
            end
        else begin
            /* Misc non-reset stuff */
            end
        if (wr) begin
            /* Writing stuff */
            end
        if (rd) begin
            /* Reading stuff */
            end
        end
    endmodule           // End OneWay

module TheOtherWay (input clock, reset, rd, wr);
    always @(posedge clock) begin: write
        if (wr) begin
            /* Writing stuff */
            end
        end
    always @(posedge clock) begin: read
        if (rd) begin
            /* Reading stuff */
            end
        end
    always @(posedge clock) begin: misc
        if (reset) begin
            /* Misc reset stuff */
            end
        else begin
            /* Misc non-reset stuff */
            end 
        end
    endmodule           // End TheOtherWay

I have two questions about this:

1. Are these two modules equivalent? In other words, is the difference between these two styles only a matter of style, or is there some subtle difference between them that actually makes a difference in how they simulate and/or synthesize?
2. In the second example, what's with the labels (write, read, and misc) on the always statements? They don't seem to be referenced anywhere, so I'm wondering if they actually do anything that a simple comment wouldn't.

Thanks,

-- Russ