I'm still messing with Verilog and the Xilinx tools and the Morse code decoder project.

I was playing with different ways to make a lookup table to convert dits and dahs after they're recognized as such into the equivalent ASCII codes, and the synthesizer seemed to be generating an awful lot of logic. So I started playing with simpler test cases and got the same result--lots more gates than actually needed to do the simplest things.

Consider this (contrived) example:

module test (
  input wire [7:0] in,
  output reg [1:0] out
  );

  always @(in) begin
    case (in)
      8'b00110001: out = 1;
      8'b10101100: out = 2;
      8'b11110101: out = 3;
      default:     out = 2'dx;
      endcase
    end
  endmodule

You can see by inspection that this requires no logic at all to implement. Just connect out[0] to in[0] and out[1] to in[7] and you're done. Yet the synthesizer spits out a network of four LUTs for this example!

Should I be surprised that the synthesizer didn't figure this out? Is there a better way to code this? Am I supposed to be doing my own logic minimization before handing things off to the tools?

-- Russ