First attempt at this shwon below. Please comment at will. I'm especially interested in these questions:

• Is the "something interesting about the assertion of the output bit" the fact that, because of the way the non-blocking assignments work, it occurs one cycle later than you might expect from a quick glance at the code?


• I struggled for a way to display the value of the counter without polluting the divide-by-N module with a bunch of test-related stuff. Is my conditional definition of the module interface reasonable? Is there a better way to make the module's guts visible to the test bench?


• There was a short discussion a long time ago about self-checking test benches that automatically give a pass/fail result so you don't have to manually wade through a bunch of output. I didn't see a real good way to do that for this exercise. Suggestions?

-- Russ

PS: I spent a long time and had to cuss a couple of times before I figured out that the little tic character on `define, `ifdef, etc., isn't a plain old apostrophe. Dang!

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Here's a rewrite of the counter itself. It includes a miniature specification at the beginning, and also parameterizes some of the magic numbers:

/* ////////////////////////////////////////////////////////////////////////////
                                     dbn.v
///////////////////////////////////////////////////////////////////////////////
DESCRIPTION:    This is a Verilog model of a divide-by-N counter.  It assumes a
                series of regular pulses on its input line, and produces pulses
                on its output at 1/N times the frequency of the input signal.

                The configurable compile time parameter MAX_COUNT sets the
                value of N.  A second parameter UP_TIME sets the duty cycle of
                the output signal.  That duty cycle is given as a percent by
                the formula (UP_TIME / MAX_COUNT) * 100.

REVISIONS:      22 Sep 07 - RAC - Genesis, following a couple of false starts.
                23 Sep 07 - RAC - Conditionally exported 'counter' for the
                                   benefit of the test bench
//////////////////////////////////////////////////////////////////////////// */

`define MAX_COUNT       10                      // Divide by this number
`define UP_TIME         3                       // Set output duty cycle to 30%
`define COUNTER_WIDTH   4                       // Enough bits to hold a value
                                                //  of MAX_COUNT, but no more
                                                //  than necessary
`ifdef ON_TEST_BENCH
module DivideByN(in, out, counter);
    input in;
    output out;
    output counter;
`else
module DivideByN(in, out);
    input in;
    output out;
`endif

    reg [`COUNTER_WIDTH-1 : 0] counter;         // Count input pulses here
    reg out;                                    // Manage output signal here

    initial begin
        counter <= 0;
        end

    always @(posedge in) begin                  // On every input pulse
        if (counter == `MAX_COUNT - 1) begin    // Time to reset the counter
            counter <= 0;                       // Do so
            end                                 // End 'time to reset counter'
        else begin                              // Not time to reset counter
            counter <= counter + 1;             // Increment it instead
            end                                 // End 'not time to reset'
        out <= counter < `UP_TIME;              // Output is high from counter
        end                                     // End 'on every input pulse'

    endmodule

Then I made a test bench, like this:

/* ////////////////////////////////////////////////////////////////////////////
                                    dbn_t.v
///////////////////////////////////////////////////////////////////////////////
DESCRIPTION:    This is a test bench for the divide-by-N counter in dbn.v

REVISIONS:      22 Sep 07 - RAC - Genesis, with hints from an online example.
//////////////////////////////////////////////////////////////////////////// */

`timescale 1ns / 1ps
`define ON_TEST_BENCH
`include "dbn.v"

module DivideByNTester ;

    reg clock;                                  // Clock to be divided
    wire dividedClock;                          // Result
    wire [`COUNTER_WIDTH-1 : 0] counter;

    initial begin
        clock <= 0;
        #60 $finish;                            // Just run for 30 clocks
        end

    always begin                                // Toggle the clock at every
        #1 clock <= ~clock;                     //  simulator tick
        end

    always @(posedge clock) begin
        $display("counter: %d, out: %d", counter, dividedClock);
        end

    DivideByN X (clock, dividedClock, counter); // Connect DUT to test bench

    endmodule

Here's the output of the simulation:

This is a Lite version of ISE Simulator.
Simulator is doing circuit initialization process.
Finished circuit initialization process.
counter:  0, out: x
counter:  1, out: 1
counter:  2, out: 1
counter:  3, out: 1
counter:  4, out: 0
counter:  5, out: 0
counter:  6, out: 0
counter:  7, out: 0
counter:  8, out: 0
counter:  9, out: 0
counter:  0, out: 0
counter:  1, out: 1
counter:  2, out: 1
counter:  3, out: 1
counter:  4, out: 0
counter:  5, out: 0
counter:  6, out: 0
counter:  7, out: 0
counter:  8, out: 0
counter:  9, out: 0
counter:  0, out: 0
counter:  1, out: 1
counter:  2, out: 1
counter:  3, out: 1
counter:  4, out: 0
counter:  5, out: 0
counter:  6, out: 0
counter:  7, out: 0
counter:  8, out: 0
counter:  9, out: 0
Stopped at time : 60.000 ns : File "C:/verilog/a/dbn_t.v" Line 23