One more question about my little counter exercise. For ease of reference, here's the Verilog source again:

`ifdef ON_TEST_BENCH
module DivideByN(in, out, counter);
    input in;
    output out;
    output counter;
`else
module DivideByN(in, out);
    input in;
    output out;

`endif
    reg [`COUNTER_WIDTH-1 : 0] counter;		// Count input pulses here
    reg out;					// Manage output signal here
    initial begin
	counter <= 0;
	end
    always @(posedge in) begin			// On every input pulse
	if (counter == `MAX_COUNT - 1) begin	// Time to reset the counter
	    counter <= 0;			// Do so
	    end					// End 'time to reset counter'
	else begin				// Not time to reset counter
	    counter <= counter + 1;		// Increment it instead
	    end					// End 'not time to reset'
	out <= counter < `UP_TIME;		// Output is high from counter
	end					// End 'on every input pulse'
    endmodule

If I synthesize this, the Xilinx tools spit out an RTL schematic that looks like this:


This looks correct to me.

Now if I change just one line of the module, so that it resets the counter to 1 instead of to 0, the tools make this schematic:


Suddenly, there's nothing connected to the output of the 4-input AND gate that detects when it's time to reset the counter, nor does it show any logic to reset the counter to 1. It does simulate as expected after the change. I also looked at the lower level "technology schematic" that shows the circuit as a network of LUTs and flip-flops, and it looks correct. It resets the counter to 1 simply enough by asserting the set input on the LSB instead of the clear.

So, am I doing something wrong, or expecting too much in thinking that the RTL schematic should be complete and correct? Or is this a result of flaky software? If you can't trust the RTL schematics generated by the synthesizer, is there some other reasonably easy way to see how it decided to implement your logic?

-- Russ