Suppose you had three MCU's, all running exactly the same code, and all controlled and stimulated by the same events. In the range at which the clocks run, the asynchronism between MCU's due to different trace lengths, and other board related artifacts are neglegible. If you had a CPLD that compared the port outputs and data bus at the rising edge of the clock, and propagated only those signals that occurred more or less simultaneously, ignoring the "odd-man" in the triumvirate, then the "odd-man" would be presumed to have failed while the other two presumably would not.

Code would have to be cyclical such that resetting the "odd-man" MCU the first time this occurred would ultimately be able to bring the three back into precise synchronization, but would, ultimately, restore the original condition, with the exception that the CPLD should, at that point, "remember" that the "odd-man" had failed and would lock him out if a failure occurred again. A signal (LED) should indicate that this latter event has occurred, thereby letting a human observer know that the system is operating in a degraded mode.

BTW, the use of only two MCU's doesn't tell you which is the errant one.

RE