I am having a little trouble with an FPGA, and I thought some of you smart folks may be able to help.

Basically I have a 2.048 MHz clock feeding a synchronous counter. Occasionally the counter advances when it shouldn't. This sounds like a glitch on the clock signal, but I have been unable to detect one using a rather fancy logic analyzer. When I replace the 74FCT244 buffer driving the clock signal with a 74LS244, the problem seems to go away. This same clock signal goes through a ferrite choke for slew rate limiting. When I short this choke, which greatly speeds up the edges of the clock signal, the problem also appears to go away. What both of these steps do is modify the phase of the clock with regard to a sync signal that periodically clears this counter. If I disable the sync signal the counter free runs perfectly, reducing the likelyhood that the problem is a glitch on clock.

Thanks in advance,

Cory Spackman