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???
06/15/01 20:47
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#12536 - RE: FPGA Glitch
The solution for this problem might be this:
feed the external clock into a latch (or a D-type flip-flop) which is clocked by the system.
I had this same (sort of) problem a few years ago with a 8255 which was preloaded to open a beer-valve for -say- 200 pulses or so (a flow-meter). I had the pulses not synchronized to the system clock and every once in a while the 8255 would shoot through the zero and start at 65535 pulses. Imagine the load of beer wasted?
When applying a latch before feeding the pulses to the 8255 the pulses met the minimal 600nS (or so) which were required for the 8255.

List of 8 messages in thread
TopicAuthorDate
FPGA Glitch            01/01/70 00:00      
RE: FPGA Glitch            01/01/70 00:00      
RE: FPGA Glitch            01/01/70 00:00      
RE: FPGA Glitch            01/01/70 00:00      
RE: FPGA Glitch            01/01/70 00:00      
RE: FPGA Glitch            01/01/70 00:00      
RE: FPGA Glitch            01/01/70 00:00      
RE: FPGA Glitch            01/01/70 00:00      

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