Maybe the sync signal appears at the
same time as a clock edge. Then setup and hold times are violated.When I use Xilinx
9500 series CPLD's, I always have a
terminal count signal or something (one-shot)output going to the Reset input of a counter to clear it. If I tie the Reset input low,
the counter will count up to its modulus or
terminal count before starting over.
I've never created a counter that didn't have a Reset input.