That should have said guess I should have PREVIEWED. FYI. I found the problem. !SYNC was cross-talking onto CLK. The event is very fast, a 333MHz logic analyzer can't see it. A 500MHz 'scope just barely sees it. I presume that if I had an even faster 'scope, I would see that the noise is much worse than I am seeing with the 500MHz 'scope. The FPGA can see it depending on where the phase relationship of the two signals puts the glitch on the rising edge of CLK. Even though !SYNC is only 8Khz the FCT family part driving the signal has very fast edges. I have recommended to the designer of the board that he separates the two traces and adds a guard trace. In the mean time we are going to use an LS family part to lower the slew rate of the signals.

Cory Spackman