Thanks for the comments.

I didn't do any of the circuit or logic design related to this problem, and I don't know the simulation results for the FPGA, but I have been assured by the designer that no timing problem exists. The counter doesn't have a reset input. It "resets" by clocking in the low on the sync line. On the falling edge of clock, if ~SYNC is low, the counter will be reset.
_ _ _ _ _ _
_| |_| |_| |_| |_| |_| |_ CLK
___________ ______
|__ | ~SYNC

The 2.048MHz clock is the system clock, so re-clocking it won't work. These two signals are two of the most fundamental in the system and are always synchronous. The ferrites perform slew rate control quite nicely, but the fact that shorting it makes the problem dissapear does make me suspicious. Series damping resistors haven't helped. One interesting thing is that when I replace the FPGA with a faster speed part, the problem seemed to lessen in severity. That would certainly suggest that it is a timing problem. I am going to see if I can get some of the fastest of these parts to see if that will eliminate the problem, not as a solution but as a diagnostic tool. I need some good data to get the designer to take another look inside the FPGA.

Cory Spackman