Hi Erik,

I found a way to be bulletproof up to 1+1/2 bit time delay:

The RI interrupt was generated in the middle of the stop bit, but the "skip_idle" jump can be done until the end of the next start bit.
With the external interrupt transition activated, it can be delayed longer. Also loosing some T1 overflow stretch only the bus free time detection a little.



Peter

        dseg
Idle_timer:     ds 1
        bseg
Bus_idle:       dbit 1
        cseg
        org     13h
intex1:
        clr     ET1
        clr     EX1
        reti
        org     1Bh
intt1:
        djnz    Idle_timer, it11
        clr     ET1
        setb    Bus_Idle        ;or AJMP to the handler
it11:   reti
        org     23h
intuart:
        jnb     RI, iu1
        clr     IE1
        jnb     RXD, skip_idle          ;work until 1+1/2 bit times delay
        mov     Idle_timer, #4 * 16     ;wait 4 bit times
        setb    ET1
        setb    EX1
skip_idle:
        clr     RI
        ; do something
        reti
iu1:    ; do something
        reti