| ??? 02/01/07 22:29 Read: times |
#131903 - Can't you support your dubious assertions? Responding to: ???'s previous message |
Erik Malund said:
and be specific
what good would that do? that would bring it back to your hammering about "my" case, where I am speaking about general issues. Yes ... that case that you presented to support your unsupportable argument. Neither repeating them nor shouting them louder will make your inherently incorrect and therefore false assertions any truer. The issue isn't very general, either. It pertains to the SiLabs series that you frequently promote and also to the DS89C4x0 series that I like to use. Are there any other 805x-core MCU's that have this cycle-stretch feature for external memory bus accesses? How can a variation in interrupt response to an externally generated process asynchronous with the internal timing, cause any more trouble in a segment of code that contains a stretched cycle, the occurrence of which YOU control, than in a similar one without a stretched cycle?
No none with such a mechanism can 'control' whether "an externally generated process asynchronous with the internal timing" happens at the start of a normal cycle or a cycle where the instruction execution speed switch (happy now) causes a delay in the response to the event. Just what is that last sentence supposed to say? BTW, the cycle-stretch is not a speed switch.
it is, see above see what above? It does, as you've pointed out, affect when interrupts are serviced. which, according to you is not a problem. According to common sense it is. Whose common sense would that be? I said it's not a problem in the case which you cited to support the silly notion that it is. Clearly, you're showing yourself to be coming up short in the "common sense" department. There's a difference between speed and timing. Speed defines the rate at which things happen, while timing defines when things happen. Consider distance and speed. Time is like distance. Speed is like, well, speed. One is the derivative of the other. So, when you're using the cycle-stretched external memory bus, as you've said you occasionally do, how do you deal with interrupts? Do you just turn 'em off? Do you send an X-OFF?
There is NOTHING here about what I do, this is general, please STOP referring to what I do, it is irrelevant!!!!!!!! so long as you can't support your putative "facts" they remain in the realm of conjecture. I am so darn sorry that I previously let you sucker me in with your darn request for examples. FACTs do not need examples. ... but if you can't produce concrete evidence, which you, up to now, haven't, your statements fall into the realm of fiction. Erik
If you'd present even ONE relevant fact, that would be a change for the better. You've said that a wait-state generator is a speed switch. It is not! It never has been. It never will be. It's like saying that a flipflop is a gate. It's not! You'd say that if you though it would support your argument, but that doesn't make it so. However, it doesn't even support your argument. The reason I demand concrete examples is because I want to make you draw a line between truth and the putative "facts" that you routinely spew forth. There is a difference between fact and fiction, just in case you've not been to a library lately. If you can't support an assertion with concrete evidence, then it's not fact! Are we supposed to accept your sometimes outrageous statements on faith? Engineering isn't based on faith. It's based on verifiable evidence. RE |
