| ??? 02/09/07 20:46 Read: times |
#132429 - not quite Responding to: ???'s previous message |
As for the ISR overhead, at F/32, and assuming 9 bits per transfer (8/N/1), that would require 9*32 = 288 clock cycles, or 288/12 = 24 machine cycles, as an upper limit on the ISR in order to insure against overrun in a sustained transmission. Correct?
not quite the answer is 24 less the interrupt latency quoting "the bible" Thus, in a single-interrupt system, the response time is always more than 3 cycles and less than 9 cycles. so an ISR running on the edge would have 15 cycles available. Erik |
| Topic | Author | Date |
| Maximum Reliable UART Baud Rates for 805x | 01/01/70 00:00 | |
| The UART in any chip with a T2 can run at F | 01/01/70 00:00 | |
| Thanks guys. | 01/01/70 00:00 | |
| not quite | 01/01/70 00:00 | |
| syntax error | 01/01/70 00:00 | |
| Point taken | 01/01/70 00:00 | |
| welcome to the club | 01/01/70 00:00 | |
| Some club ... | 01/01/70 00:00 | |
| they just were too square :) | 01/01/70 00:00 | |
Mmmh, yeah, well ... | 01/01/70 00:00 | |
| not necessarily | 01/01/70 00:00 | |
| Polling | 01/01/70 00:00 | |
| not only this... | 01/01/70 00:00 | |
| Scheme | 01/01/70 00:00 | |
| isn't it the same? | 01/01/70 00:00 | |
| polling all the way | 01/01/70 00:00 | |
| Wrong question? | 01/01/70 00:00 | |
| define maximum rate... | 01/01/70 00:00 | |
| semantics | 01/01/70 00:00 | |
| for the standard '51/'52... | 01/01/70 00:00 | |
| HUH | 01/01/70 00:00 | |
| PC | 01/01/70 00:00 | |
| non-standard | 01/01/70 00:00 | |
| Why comes in UART on PC and 232 buffer? | 01/01/70 00:00 | |
| sorry | 01/01/70 00:00 | |
| Good note | 01/01/70 00:00 | |
| OK I take back | 01/01/70 00:00 | |
| CP210x USB-UART | 01/01/70 00:00 |