The master is easy, it knows when to talk. The slave is more difficult, it must be ready to talk when the master speaks. Thus, while you can bit bang a master in a simple loop (the overhead is less when using a timer), that will not work for slaves (well, it will, but the communication will be horredously variable). Thus, in the slave, you need an interrupt pin to 'detect' master communications and then you have to switch to looped sense. It's been so long, but I seem to recall that to handle one condition efficiently you need both SDA and SCL connevted to each an interrupt pin. Again, you do not NEED to connect anything to an interrupt, the IIC master WILL wait, but the timing impact will lead to 'funny things' elsewhere most likely

Yes, it IS possible, but why not save yourself a lot of troubke and go for a derivative with HW IIC, even the $1 LPCs fro NXP have HW IIC.

Then you gain two things a) 'free' working code (CodeArchitect, free from esacademy) no horrendous overhead from bit-banging. In the pre HW IIC days, I did a bit-banged MS system and, boy, did I lose some hair and was the result 'great'? by no means, but, as stated, it did work.

to get a selection of derivatives with HW IIC use the Keil device database

http://www.keil.com/dd/parm_search.asp

Erik

PS with 15 minutes of work the CodeArchitect code for HW IIC can be mane work on all non-NXP derivatives I know of, except the SILabs deviates (F3x -up)