While nWR is useable as a rising_edge clock when writing data to external memory or I/O, the spec's can be confusing. ALE is not really useable as a clock to a clocked address register because the addressed become valid during but not before ALE and registers require setup time. Latches, e.g. 'LS373 require no setup time, but do require a specified hold time after the gate strobe, presumably ALE in this case, goes false. The 805x family provides this hold time, but the ALE itself is a poor choice of signals to use as a clock to any sort of clocked element associated with addressing/decoding.

Likewise nPSEN and nRD are output enables intended to be used in transactions that require some predefined hold time after they are negated (after they, both negative-going signals, go positive. The MCU samples the data inputs before they go positive. I can't immediately think of a way in which they'd be helpful in any way as a clock, as data is not required to be valid at their falling edge, nor would it necessarily remain valid long after their respective rising edges.

Keep in mind, too, that ALE occurs twice on each external program memory fetch cycle, but only once for a cycle accessing external data memory or external memory-mapped I/O.

If you're concerned about the effect of track width on signal quality, theres an old book that you may find in a library, which is the Motorola MECL Design Handbook, mostly written a fellow named Blood. This work is considered the definitive work on PCB signal quality even today, and much of the software written for the purpose of analysis and simulation of signal quality on PCB traces and used in IBIS and other such tools is largely based on in. Around here, this book, out of print for many years, has been lost by most libraries, so it's quite rare. If you find one, you should read it thoroughly, at least twice, as it dealt, back in the days when ECL was the only fast logic family, with the PCB signal quality issues that are of concern to everyone nowadays.

RE